Addition to “ A Wideband 2 . 4 - GHz Delta - Sigma Fractional - PLL With 1 - Mb / s In - Loop Modulation ”

نویسنده

  • Sudhakar Pamarti
چکیده

[1] I. Bietti, E. Ternporitil, G. Albasini, and R. Castello, “An UMTS sigma delta fractional synthesizer with 200 kHz bandwidth and 128 dBc/Hz at 1 MHz using spurs compensation and linearization techniques,” in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2003, pp. 463–466. [2] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49–62, Jan. 2004.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Delta-Sigma Fractional-N Phase-Locked Loops

This paper presents a tutorial on delta-sigma fractional-N PLLs for frequency synthesis. The presentation assumes the reader has a working knowledge of integer-N PLLs. It builds on this knowledge by introducing the additional concepts required to understand ΔΣ fractional-N PLLs. After explaining the limitations of integerN PLLs with respect to tuning resolution, the paper introduces the delta-s...

متن کامل

Delta-Sigma Modulation in Fractional-N Frequency Synthesis

This paper describes a delta-sigma ( A-Z ) modulation and fractional-S frequency division technique to perform indirect digital frequency synthesis based on the use of a phaselocked loop (PLL). The use of 1 Y modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-S division. The technique has the potential to provide low phase noise, fast ...

متن کامل

Phase noise and jitter modeling for fractional-N PLLs

Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase n...

متن کامل

Delta - Sigma Modulator PLLs With Dithered Divide - Ratio

A phase-locked loop (PLL) with frequency resolution in steps smaller than the reference oscillator is often wanted. Although this can be accomplished with a fractional-N PLL, in which the divide ratio is varied between N and N+1 at a defined rate, this technique generates undesired spurs. An alternative is to use a delta-sigma modulator in which the divide ratio (divisor) is dithered, eliminati...

متن کامل

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2005